Doubling the data rate often increases power per bit. However, the spec includes aggressive power management states (L0p sub-states) to shut down unused lanes dynamically.
This article explores everything you need to know about the spec, where to find the official document, and the revolutionary changes contained within its pages. pci express base specification revision 60 pdf
Anyone speccing out an AI cluster or High-Performance Computing (HPC) solution needs to understand the implications of L0p for power budgeting and FLIT for CXL 3.0 coherency. Doubling the data rate often increases power per bit
The defining achievement of PCIe 6.0 is its raw speed. It delivers up to 64 Gigatransfers per second (GT/s) per lane. where to find the official document